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8 Mbit (x8) Multi-Purpose Flash
SST39LF080 / SST39VF080
SST39LF/VF0803.0 & 2.7V 8Mb (x8) MPF memories
EOL Data Sheet
FEATURES:
* Organized as 1M x8 * Single Voltage Read and Write Operations - 3.0-3.6V for SST39LF080 - 2.7-3.6V for SST39VF080 * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 14 MHz) - Active Current: 12 mA (typical) - Standby Current: 4 A (typical) - Auto Low Power Mode: 4 A (typical) * Sector-Erase Capability - Uniform 4 KByte sectors * Block-Erase Capability - Uniform 64 KByte blocks * Fast Read Access Time: - 55 ns for SST39LF080 - 70 and 90 ns for SST39VF080 * Latched Address and Data * Fast Erase and Byte-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Chip Rewrite Time: 15 seconds (typical) for SST39LF/VF080 * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 40-lead TSOP (10mm x 20mm) - 48-ball TFBGA (6mm x 8mm)
PRODUCT DESCRIPTION
The SST39LF/VF080 devices are 1M x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF080 write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF080 write (Program or Erase) with a 2.7-3.6V power supply. They conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF/ VF080 devices provide a typical Byte-Program time of 14 sec. The devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39LF/VF080 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alter(c)2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
native flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39LF/VF080 are offered in 40-lead TSOP and 48ball TFBGA packages. See Figures 1 and 2 for pin assignments.
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39LF/VF080 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 15 mA to typically 4 A. The Auto Low Power mode reduces the typical IDD active read current to the range of 1 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto Low Power mode after power-up with CE# held steadily low until the first address transition or CE# is driven high.
operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39LF/VF080 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform block size of 64 KByte. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.
Read
The Read operation of the SST39LF/VF080 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3).
Chip-Erase Operation
The SST39LF/VF080 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Byte-Program Operation
The SST39LF/VF080 are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the ByteProgram operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 s. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program
Write Operation Status Detection
The SST39LF/VF080 provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.
(c)2007 Silicon Storage Technology, Inc.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Data Protection
The SST39LF/VF080 provide both hardware and software features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Data# Polling (DQ7)
When the SST39LF/VF080 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 17 for a flowchart.
Software Data Protection (SDP)
The SST39LF/VF080 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST39LF/VF080 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart.
Common Flash Memory Interface (CFI)
The SST39LF/VF080 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must load the three-byte sequence, similar to the Software ID Entry command. The last byte cycle of this command loads 98H (CFI Query command) to address 5555H. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.
(c)2007 Silicon Storage Technology, Inc.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
Product Identification
The Product Identification mode identifies the device as SST39LF080 or SST39VF080 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 18 for the Software ID Entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST39LF/VF080 0001H D8H
T1.3 1146
Product Identification Mode Exit/ CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure 18 for a flowchart.
Data BFH
0000H
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffer & Latches Y-Decoder
CE# OE# WE# DQ7 - DQ0
1146 B1.2
Control Logic
I/O Buffers and Data Latches
(c)2007 Silicon Storage Technology, Inc.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
A16 A15 A14 A13 A12 A11 A9 A8 WE# NC NC NC A18 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Standard Pinout Top View Die Up
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 1146 F01.3
FIGURE 1: Pin Assignments for 40-lead TSOP
TOP VIEW (balls facing down)
6 5 4 3 2 1
A14 A13 A15 A9 A8 A11 NC NC A6 A2
A16 A17 NC
NC VSS
A12 A19 A10 DQ6 DQ7 NC DQ5 NC VDD DQ4
1146 48-tfbga P2.2
WE# NC NC A7 A3 NC A18 A4
NC DQ2 DQ3 VDD NC A5 A1 DQ0 NC NC DQ1
A0 CE# OE# VSS
A
B
C
D
E
F
G
H
FIGURE 2: Pin Assignments for 48-ball TFBGA
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet TABLE 2: PIN DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Pin Name Address Inputs Data Input/output Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 3.0-3.6V for SST39LF080 2.7-3.6V for SST39VF080
CE# OE# WE# VDD VSS NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
Unconnected pins.
T2.4 1146
1. AMS = Most significant address AMS = A19 for SST39LF/VF080
TABLE 3: OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 4
T3.4 1146
CE# VIL VIL VIL VIH X X
OE# VIL VIH VIH X VIL X
WE# VIH VIL VIL X X VIH
DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT
Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X
1. X can be VIL or VIH, but no other value.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Block-Erase Chip-Erase Software ID Entry4,5 CFI Query Entry4 Software ID CFI Exit Exit6/ 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H XXH 5555H Data AAH AAH AAH AAH AAH AAH F0H AAH 2AAAH 55H 5555H F0H
T4.4 1146
2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H Data A0H 80H 80H 80H 90H 98H
4th Bus Write Cycle Addr1 WA2 5555H 5555H 5555H Data Data AAH AAH AAH
5th Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data 55H 55H 55H
6th Bus Write Cycle Addr1 SAX3 BAX
3
Data 30H 50H 10H
5555H
Software ID Exit6/ CFI Exit
1. Address format A14-A0 (Hex), Addresses A19-A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF080. 2. WA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines BAX for Block-Erase; uses AMS-A16 address lines AMS = Most significant address AMS = A19 for SST39LF/VF080 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer's ID = BFH, is read with A0 = 0 SST39LF/VF080 Device ID = D8H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent
TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/VF080
Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 51H 52H 59H 01H 07H 00H 00H 00H 00H 00H 00H Data Query Unique ASCII string "QRY"
Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits)
T5.4 1146
1. Refer to CFI publication 100 for more details.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39LF/VF080
Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 27H1 30H1 36H 00H 00H 04H 00H 04H 06H 01H 00H 01H 01H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min (00H = no VPP pin) VPP max (00H = no VPP pin) Typical time out for Byte-Program 2N s (24 = 16 s) Typical time out for min size buffer program 2N s (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (26 = 64 ms) Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 s) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T6.2 1146
1. 0030H for SST39LF080 and 0027H for SST39VF080
TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF080
Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 14H 00H 00H 00H 00H 02H FFH 00H 10H 00H 0FH 00H 00H 01H Data Device size = 2N Bytes (14H = 20; 220 = 1 MByte) Flash Device Interface description; 0000H = x8-only asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 255 + 1 = 256 sectors (00FFH = 255) z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 15 + 1 = 16 blocks (000FH = 15) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.0 1146
(c)2007 Silicon Storage Technology, Inc.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE FOR SST39LF080
Range Commercial Ambient Temp 0C to +70C VDD 3.0-3.6V
OPERATING RANGE FOR SST39VF080
Range Commercial Industrial Ambient Temp 0C to +70C -40C to +85C VDD 2.7-3.6V 2.7-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF080 Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF080 See Figures 14 and 15
(c)2007 Silicon Storage Technology, Inc.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet TABLE 8: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF080 AND 2.7-3.6V FOR SST39VF0801
Limits Symbol IDD Parameter Power Supply Current Read2 Program and Erase ISB IALP ILI ILO VIL VILC VIH VIHC VOL VOH Standby VDD Current Auto Low Power Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 0.2 20 30 20 20 1 10 0.8 0.3 mA mA A A A A V V V V V V Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD Max CE#=VILC, VDD=VDD Max All inputs=VSS or VDD, WE#=VIHC VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T8.7 1146
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25C (room temperature), and VDD = 3V for VF devices. Not 100% tested. 2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Program/Erase Operation
Minimum 100 100
Units s s
T9.1 1146
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: CAPACITANCE (Ta = 25C, f=1 Mhz, other pins open)
Parameter CI/O
1
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T10.0 1146
CIN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
1,2
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T11.2 1146
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
AC CHARACTERISTICS
TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF080 AND 2.7-3.6V FOR SST39VF080
SST39LF080-55 Symbol Parameter TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ TOH1
1
SST39VF080-70 Min 70 Max 70 70 35 0 0
SST39VF080-90 Min 90 90 90 45 0 0 Max Units ns ns ns ns ns ns 30 30 0 ns ns ns
T12.4 1146
Min 55
Max 55 55 30
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change
0 0 15 15 0
20 20 0
TOHZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH1 TDS TDH1 TIDA1 TSE TBE TSCE Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase 0 30 0 0 0 10 40 40 30 30 30 0 150 25 25 100 Min Max 20 Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms
T13.0 1146
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
TRC
TAA
ADDRESS AMS-0 TCE CE# TOE OE# VIH WE# HIGH-Z DQ7-0 TCLZ TOH DATA VALID TCHZ HIGH-Z DATA VALID TOLZ TOHZ
1146 F02.2
FIGURE 3: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TWP WE# TAS OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA)
1146 F03.2
2AAA
5555
ADDR TDH
TWPH
TDS
FIGURE 4: WE# Controlled Program Cycle Timing Diagram
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TCP CE# TAS OE# TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TCPH TDS 2AAA 5555 ADDR TDH
1146 F04.2
FIGURE 5: CE# Controlled Program Cycle Timing Diagram
ADDRESS AMS-0 TCE CE# TOEH OE# TOE WE# TOES
DQ7
DATA
DATA#
DATA#
DATA
1146 F05.2
FIGURE 6: Data# Polling Timing Diagram
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
13
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
ADDRESS AMS-0 TCE CE# TOEH OE# TOE TOES
WE#
DQ6
TWO READ CYCLES WITH SAME OUTPUTS
1146 F06.2
FIGURE 7: Toggle Bit Timing Diagram
SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
1146 F08.3
FIGURE 8: WE# Controlled Chip-Erase Timing Diagram
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
14
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA BAX
TBE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
50 SW5
1146 F09.3
FIGURE 9: WE# Controlled Block-Erase Timing Diagram
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX
TSE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
1146 F10.3
FIGURE 10: WE# Controlled Sector-Erase Timing Diagram
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
15
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
CE#
OE# TWP WE# TWPH DQ7-0 AA SW0
Note:
TIDA
TAA 90 SW2 BF Device ID
1146 F11.4
55 SW1
Device ID = D8H for SST39LF/VF080
FIGURE 11: Software ID Entry and Read
THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
CE#
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 98
1146 F12.0
TIDA
TAA
SW2
FIGURE 12: CFI Query Entry and Read
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
16
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
AA
55
F0 TIDA
CE#
OE# TWP WE# TWHP SW0 SW1 SW2
1146 F13.0
FIGURE 13: Software ID Exit/CFI Exit
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1146 F14.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 14: AC Input/Output Reference Waveforms
TO TESTER
TO DUT CL
1146 F15.1
FIGURE 15: A Test Load Example
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
18
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
Start
Load data: AAH Address: 5555H
Load data: 55H Address: 2AAAH
Load data: A0H Address: 5555H
Load Byte Address/Byte Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
1146 F16.1
FIGURE 16: Byte-Program Algorithm
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
19
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
Internal Timer Program/Erase Initiated
Toggle Bit Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE, TSE or TBE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes Program/Erase Completed
Program/Erase Completed
1146 F17.0
FIGURE 17: Wait Options
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
20
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
CFI Query Entry Command Sequence
Software Product ID Entry Command Sequence
Software ID Exit/CFI Exit Command Sequence
Load data: AAH Address: 5555H
Load data: AAH Address: 5555H
Load data: AAH Address: 5555H
Load data: F0H Address: XXH
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Wait TIDA
Load data: 98H Address: 5555H
Load data: 90H Address: 5555H
Load data: F0H Address: 5555H
Return to normal operation
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Software ID
Return to normal operation
1146 F18.1
FIGURE 18: Software ID/CFI Command Flowcharts
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
21
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
Chip-Erase Command Sequence Load data: AAH Address: 5555H
Sector-Erase Command Sequence Load data: AAH Address: 5555H
Block-Erase Command Sequence Load data: AAH Address: 5555H
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Load data: 80H Address: 5555H
Load data: 80H Address: 5555H
Load data: 80H Address: 5555H
Load data: AAH Address: 5555H
Load data: AAH Address: 5555H
Load data: AAH Address: 5555H
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Load data: 10H Address: 5555H
Load data: 30H Address: SAX
Load data: 50H Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased to FFH
Sector erased to FFH
Block erased to FFH
1146 F19.1
FIGURE 19: Erase Command Sequence
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
22
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
PRODUCT ORDERING INFORMATION
SST 39 XX VF 080 XX XXXX - 70 - XXX 4C XX - B3K - XXX E X Environmental Attribute E = non-Pb Package Modifier I = 40 leads K = 48 balls Package Type B3 = TFBGA (0.8mm pitch, 6mm x 8mm) E = TSOP (type 1, die up, 10mm x 20mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 55 = 55 ns 70 = 70 ns 90 = 90 ns Device Density 080 = 8 Mbit Voltage L = 3.0-3.6V V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash
Valid combinations for SST39LF080 SST39LF080-55-4C-EI SST39LF080-55-4C-EIE SST39LF080-55-4C-B3K SST39LF080-55-4C-B3KE
Valid combinations for SST39VF080 SST39VF080-70-4C-EI SST39VF080-70-4C-EIE SST39VF080-90-4C-EI SST39VF080-90-4C-EIE SST39VF080-70-4I-EI SST39VF080-70-4I-EIE SST39VF080-90-4I-EI SST39VF080-90-4I-EIE SST39VF080-70-4C-B3K SST39VF080-70-4C-B3KE SST39VF080-90-4C-B3K SST39VF080-90-4C-B3KE SST39VF080-70-4I-B3K SST39VF080-70-4I-B3KE SST39VF080-90-4I-B3K SST39VF080-90-4I-B3KE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
23
8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
PACKAGING DIAGRAMS
1.05 0.95 Pin # 1 Identifier 0.50 BSC
10.10 9.90
0.27 0.17
18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80
0.15 0.05
0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50
1mm 40-tsop-EI-7
FIGURE 20: 40-lead Thin Small Outline Package (TSOP) 10mm x 20mm SST Package Code: EI
(c)2007 Silicon Storage Technology, Inc.
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8 Mbit Multi-Purpose Flash SST39LF080 / SST39VF080
EOL Data Sheet
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
6 5 4 3 2 1
0.80 ABCDEFGH A1 CORNER HGFEDCBA 4.00 6.00 0.20
6 5 4 3 2 1
SIDE VIEW
1.10 0.10
A1 CORNER
SEATING PLANE 0.35 0.05
0.12
1mm
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-4
FIGURE 21: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm SST Package Code: B3K
TABLE 14: REVISION HISTORY
Number 03 04 Description Date May 2002 Mar 2003
* * * *
2002 Data Book B3K package no longer offered for SST39LF/VF016 Part number changes - see page 23 for additional information Changes to Table 8 on page 10 - Added footnote for MPF power usage and Typical conditions - Changed the IALP test onditions - Clarified the test conditions for Power Supply Current and Read parameters - Corrected the IDD Read Current from 15 mA to 20 mA - Corrected the IDD Program and Erase Current from 20 mA to 30 mA Removed 16 Mbit parts (SST39LF/VF016); refer to SST39VF1681/1682 (S71243) 2004 Data Book Updated B3K package diagram End of Life Data Sheet for all devices in S71146
05 06 07
* * * *
Aug 2003 Nov 2003 June 2007
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07
25

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